1. Field of the Invention
The present invention relates to a solid state image sensor employing an array of pixels, each pixel comprising a photodiode and a plurality of insulated gate transistors such as MOSFETs.
2. Description of the Related Art
There are various solid state image sensors that employ semiconductor devices such as solid state charge-coupled devices (CCDs). The CCD image converters have an interline transfer (IT-CCD), a frame transfer (FT-CCD), charge primitive device (CPD), a photoconductive layer on solid scanner (PLOSS) and other structures. Among them, the interline transfer CCD architecture arranges transfer CCDs between photodiodes.
FIG. 1 shows an example of the interline transfer CCD image sensor according to a prior art. In FIG. 1, photodiodes 103 simultaneously transfer accumulated charge to vertical CCDs (V-CCD) 101-1 to 101-n, which transfer the charge of each line of the photodiodes 103 to a horizontal CCD (H-CCD) 104. The horizontal CCD 104 serially transmits data based on the transferred charge to the outside through an amplifier 105.
This prior art needs a high voltage of about 10 V to read signal charge from the photodiodes 103, as well as power supplies of zero and minus volts to transfer the signal charge. Then the prior art consumes large power and further has a problem that the CCDs are hardly installed on a chip.
To solve the problem, image sensors employing MOSFETs are attracting attention. The MOS type image sensor arranges address lines in a matrix form to select pixels each consisting of a photodiode, MOSFET switching elements, etc.
FIG. 2 shows the structure of a pixel of an image sensor employing the MOSFETs. A photodiode D30 converts light into a photodiode current, which passes through a load transistor Q31. This current is about 10.sup.-15 A to 10.sup.-9 A. Accordingly, the load MOSFET Q31 operates in a weak inversion region, i.e., a sub-threshold mode (Vc &lt;&lt;Vth), and conversion from a photoelectric current into a voltage is dependent on a logarithmic value of a current value. A source voltage of the load MOSFET Q31 is buffered by a source-follower MOSFET Q32. A pixel selection MOSFET Q33 is connected to an activation line 215 and a data read line 216.
When the MOS type image sensor employs miniaturized feature sizes, each MOSFET involves a short gate length to make a short-channel effect conspicuous. This increases a leakage current between the source region and drain region of the load MOSFET Q31, to deteriorate the sensitivity of the pixel.
To suppress a "punch through" phenomenon between the source and drain regions of a MOS transistor in a weak inversion region, Japanese Unexamined Patent Publication No. 9-298286 discloses a technique of extending the gate length of the load MOSFET Q31. This technique, however, contradicts fine element technology and has some limitations.
Namely, this technique maintains the impurity concentration of well regions and extends the gate length of the load MOSFET Q31 by 1.1 times or larger. If finer design rules are employed, the technique must increase the impurity concentration of well regions.
To suppress the punch through phenomenon between the source and drain regions of a MOS transistor in a weak inversion region, the impurity concentration of well regions must be increased. The photodiode D30 for converting light into carriers, however, is formed in the same p-well region where the load MOSFET Q31 is formed.
Namely, an anode region of the photodiode D30 is in the p-well region, and a cathode region thereof is in an n-diffusion layer that is formed in the p-well region. This n-diffusion layer serves as the source/drain region of the load MOSFET Q31. If the impurity concentration of the p-well region is increased, the impurity concentration of the n-diffusion layer must also be increased to maintain a specific I-V characteristics of MOSFET realizing a predetermined saturation signal quantity. This makes a junction electric field steeper to increase so called "white pixels" due to junction leakage currents. In addition, this makes a junction shallower to deteriorate spectral sensitivity in a long wavelength spectrum and increase a signal read voltage.